Stafic versus Dynamic power Losses in CMOS Considering Temperature VLSI S 1 - stems
نویسندگان
چکیده
The static power consumprion is analysed with taking into account reverse biased p_n jun;ti; current and MOSFET leakage current. The p_n junction reverse current is assessed as a sum of saturation I, and generation I*.n .o,r,fon"nrr. fl. donrinant leakage cument of MId structirc for deep s,ubmigro.n technologies is subthrc_sholA .rrrcnt I,"u [2], thus this. is the only con'lponcnt considc.rcd. Authors have analyscd energy collcctcd by junction and MIS capacitance in Cl\{OS invcrtci lthc cftbct of gate switching rvas takcn inro considr_rariony [+1. Thc static pou.e,r losscs (causc_d by't,, t.",,. and lru6) arc comparcd to thc capacitancc .tor-,:ingiair.no.gini losscs for rhc' sanic clc,nicnt. i.e. p_n j;;;;"" or MoS transistor.
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